Overview
- Explores how Large Language Models (LLMs) can be applied to hardware design and security
- Provides step-by-step demonstrations of LLM-assisted tasks in Verilog, SystemVerilog generation
- Includes real examples, step-by-step methodologies and hands-on applications
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About this book
This book provides a comprehensive guide to using LLMs for secure and efficient chip design, addressing key aspects such as LLM-driven IP development, verification, threat modeling, property generation, and security validation. The authors explore how LLMs can be harnessed for hardware IP verification, security assurance, and protection against emerging threats such as hardware Trojans, side-channel attacks, and supply chain vulnerabilities. By covering both the foundations of SoC design and security and the practical applications of LLMs in IP protection, this book will serve as an essential reference for hardware engineers, security researchers, SoC designers, and IP vendors seeking to integrate AI-driven methodologies into their workflow. The book not only presents the theoretical foundations of using LLMs in chip design but also provides practical insights into real-world implementation, ensuring that readers can apply these techniques effectively in securing next-generation semiconductor devices.
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Table of contents (8 chapters)
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Front Matter
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Back Matter
Editors and affiliations
About the editors
Farimah Farahmandi is an assistant professor in the Department of ECE at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of ECE at the University of Tehran, Iran in 2010 and 2013, respectively. Her research interests include design automation of System-on-Chips and energy-efficient systems, formal verification, hardware security validation, and post-silicon validation and debug. Her research has resulted in two books, seven book chapters, and several publications in premier ACM/IEEE journals and conferences, including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards, including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, a nomination for the Best Paper Award in ASP-DAC 2017, and DAC Richard Newton Young Student Fellowship. She has actively collaborated with various research groups (IBM, Intel, and Cisco) that have led to several joint publications. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She also has served on many technical program committees as well as organizing committees of premier ACM and IEEE conferences. Her research has been sponsored by SRC, AFRL, DARPA, and Cisco. She is a member of IEEE and ACM.
Jingbo Zhou is a Post-Doctoral Research Associate in the Department of ECE at the University of Florida. He received his Ph.D. degree from the Ohio State University in 2023. Prior to that, he received his B.Eng. degree in telecommunication engineering from Beijing University of Post and Telecommunication, Beijing, China in 2018. His research interests include hardware security in system in package (SiP), side-channel attack protection, SoC design testing and large language model (LLM)-assisted secure circuit design.
Upoma Das is a Postdoctoral Research Associate in the Department of ECE at the University of Florida. She received her Ph.D. degree in ECE from the University of Florida in 2025. Prior to that, she received her M.S. degree in ECE from the University of Florida in 2023 and her B.Sc. degree in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology (BUET), Dhaka, Bangladesh, in 2018. Her research interests include side-channel analysis, fault injection attacks, and large language model (LLM)-assisted hardware design and verification.
Sujan Kumar Saha is a Post-Doctoral Research Associate in the Department of ECE at the University of Florida. He received his Ph.D. degree from University of Florida in 2023. Prior to that, he received his B.Sc degree on electrical and electronic engineering from Bangladesh University of Engineering and technology (BUET) in 2011, M.Sc on computer engineering from University of California, Riverside. His research interest includes system-on-chip (SoC) security, FPGA security, and large language model (LLM)-guided secure SoC design.
Mark Tehranipoor is the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering at the University of Florida. His current research projects include hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. He has published 400+ journal articles and refereed conference papers and has given 220+ invited talks and keynote addresses. In addition, he has 19 patents issued, 22 pending invention disclosures, and has published 16 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies. He has also served as Program Chair of several IEEE/ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, etc.). He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST). He is a Fellow of IEEE, a Fellow of ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE Computer Society, and a Member of ACM SIGDA.
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Bibliographic information
Book title: LLM for SoC Design and Security
Editors: Farimah Farahmandi, Jingbo Zhou, Upoma Das, Sujan Kumar Saha, Mark Tehranipoor
DOI: https://doi.org/10.1007/978-3-032-34116-7
Publisher: Springer Cham
eBook packages: Engineering, Engineering (R0)
Copyright information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2027
Hardcover ISBN: 978-3-032-34115-0Published: 16 October 2026
Softcover ISBN: 978-3-032-34118-1Due: 30 October 2027
eBook ISBN: 978-3-032-34116-7Published: 15 October 2026
Edition number: 1
Number of pages: XI, 250
Number of illustrations: 1 b/w illustrations